| [ CnUnix ] in KIDS 글 쓴 이(By): 구르미 (구르미) 날 짜 (Date): 2007년 10월 11일 목요일 오후 09시 11분 50초 제 목(Title): Re: [Q] Intel CPU 들의 TLB entries 갯수? Chapter 10.1 Instruction TLB (4-KByte Pages) . Pentium 4 and Intel Xeon processors: 128 entries, 4-way set associative. . Intel Core 2 Duo, Intel Core Duo, Intel Core Solo processors, Pentium M processor: 128 entries, 4-way set associative. . P6 family processors: 32 entries, 4-way set associative. . Pentium processor: 32 entries, 4-way set associative; fully set associative for Pentium processors with MMX technology. Data TLB (4-KByte Pages) . Intel Core 2 Duo processors: DTLB0, 16 entries, DTLB1, 256 entries, 4 ways. . Pentium 4 and Intel Xeon processors: 64 entries, fully set associative; shared with large page data TLBs. . Intel Core Duo, Intel Core Solo processors, Pentium M processor: 128 entries, 4-way set associative. . Pentium and P6 family processors: 64 entries, 4-way set associative; fully set, associative for Pentium processors with MMX technology. Instruction TLB (Large Pages) . Intel Core 2 Duo processors: 4 entries, 4 ways. . Pentium 4 and Intel Xeon processors: large pages are fragmented. . Intel Core Duo, Intel Core Solo, Pentium M processor: 2 entries, fully associative. . P6 family processors: 2 entries, fully associative. . Pentium processor: Uses same TLB as used for 4-KByte pages. Data TLB (Large Pages) . Intel Core 2 Duo processors: DTLB0, 16 entries, DTLB1, 32 entries, 4 ways. . Pentium 4 and Intel Xeon processors: 64 entries, fully set associative; shared with small page data TLBs. . Intel Core Duo, Intel Core Solo, Pentium M processor: 8 entries, fully associative. . P6 family processors: 8 entries, 4-way set associative. . Pentium processor: 8 entries, 4-way set associative; uses same TLB as used for 4-KByte pages in Pentium processors with MMX technology. |